Week 1 - nMOSFET and Inverter Characteristics

nMOSFET EQs

A diagram for the following is shown below:

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K_{n} = K_{n}^{'} \cdot \frac{W}{L}, K_{n}^{'} = μ_{n} C_{o x}^{″} = μ_{n} \frac{ϵ_{o x}}{t_{o x}}, I_{G} = 0, I_{B} = 0

Cutoff Region, when $V_{G S} \leq V_{t n}$ :

V_{G S} \leq V_{t n} \Rightarrow I_{D} = 0

Triode Region*, when $V_{G S} - V_{t n} \geq V_{D S} \geq 0$ :

I_{D} = K_{n} ((V_{G S} - V_{t n}) V_{D S} - \frac{1}{2} V_{D S}^{2})

Saturation Region, when $V_{D S} \geq V_{G S} - V_{t n} = V_{O V} \geq 0$ . If ideal, then $λ = 0$ :

I_{D} = \frac{K_{n}}{2} (V_{G S} - V_{t n})^{2} (1 + λ V_{D S})

The Threshold Voltage $V_{t n}$ is calculated via:

V_{t n} = V_{t o} + γ (\sqrt{v_{S B} + 2 ϕ_{F}} - \sqrt{2 ϕ_{F}})

Where $ϕ_{F}$ is the flat-band voltage of the ENMOS, seen in [[EE 306 MOSFETs Equation Sheet Fall 2023.pdf]], and $γ$ is the Body-effect parameter for the ENMOS.

Inverter Characteristics

$V_{L}$ The nominal voltage corresponding to low-logic state at the output when $V_{I} = V_{H}$ . Generally, $V_{-} \leq V_{L}$ .
$V_{H}$ The nominal voltage corresponding to high-logic state at the output when $V_{I} = V_{L}$ . Generally $V_{+} \geq V_{H}$ .
$V_{I L}$ The max input voltage recognized as a low logic signal
$V_{I H}$ The min input voltage recognized as a high logic signal
$V_{O H}$ The output voltage corresponding to an input voltage of $V_{I L}$
$V_{O L}$ The output voltage corresponding to an input voltage of $V_{I H}$

N M_{L} = V_{I L} - V_{O L}

N M_{H} = V_{O H} - V_{I H}

$t_{r}$ : rise time from $V_{10 %}$ to $V_{90 %}$ .
$t_f: fall time from $V_{90 %}$ to $V_{10 %}$ .

V_{10 %} = V_{L} + 0.1 Δ V

V_{90 %} = V_{L} + 0.9 Δ V = V_{H} - 0.1 Δ V

Δ V = V_{H} - V_{L}

$τ_{P}$ : Propagation delay, difference in time from input/output signals reaching their 50% mark
$τ_{P H L}$ : high-to-low output transition time
$τ_{P L H}$ : low-to-high output transition time

V_{50 %} = \frac{V_{H} + V_{L}}{2}

τ_{P} = \frac{τ_{P L H} + τ_{P H L}}{2}

PDP: Power Delay product. $P$ is the average power dissipated by the logic gate.

P D P = P τ_{P}