HW 5 - CMOS Inverter Dynamic and Power Energy Characteristics

7.3: CMOS Inverter Dynamic Characteristics

1

We can find the Kn′ and Kp′ via:

Kn′=μnCox=μn⋅εoxtox

and similar for the PMOS. Here εox=3.9⋅8.854⋅10−14F/cm=345.3fF/cm, and we have tox=100 Angstoroms =10nm:

Kn′=500cm2Vs⋅345.3fF / cm10−6 cm =173μA/V2

and:

Kp′=200cm2Vs⋅345.3fF / cm10−6 cm =69.1μA/V2

24

a

We know that:

τPHL=1.2C⋅1Kn(VH−Vtn)τPLH=1.2C⋅1Kp(VH+Vtp)

and:

tf=3τPHL,tr=3τPLH

where here VDD=VH=2.5V. Notice that:

Kn=Kn′⋅(W/L)N=100μA/V2⋅2=200μA/V2

and:

Kp=Kp′⋅(W/L)P=40μA/V2⋅5=200μA/V2

Thus:

τPHL=1.2⋅0.20⋅10−12F⋅1200μA/V2⋅(2.5V−0.6V)=0.632 nsτPLH=1.2⋅0.20⋅10−12F⋅1200μA/V2⋅(2.5V−0.6V)=0.632 ns

therefore τP=0.632 ns by symmetry. Furthermore:

tf=3τPHL=tr=3τPLH=1.896 ns

b and c

The same calculations apply, just change VDD=2.0V and VDD=1.8V respectively:

τP=1.2⋅0.20⋅10−12F⋅1200μA/V2⋅(2.0V−0.6V)=0.857 ns

then:

tr=tf=2.57 ns

and for c:

τP=1 ns

then:

tr=tf=3 ns

27

Use the same formula as prior:

Kn=2⋅100μA/V2=200μA/V2Kp=2⋅40μA/V2=80μA/V2

thus:

τPHL=1.2⋅0.4⋅10−12F⋅1200μA/V2⋅(2.5V−0.6V)=1.264 nsτPLH=1.2⋅0.4⋅10−12F⋅180μA/V2⋅(2.5V−0.6V)=3.158 ns

so:

τP=τPHL+τPLH2=2.211 ns

and:

tf=3τPHL=3.792 nstr=3τPLH=9.474 ns

29

Again just use the same formula:

Kn=2⋅100μA/V2=200μA/V2Kp=5⋅40μA/V2=200μA/V2

by the symmetry of Kn,Kp as well as Vtn,Vtp then we'll have τP=τPHL=τPLH:

τp=1.2⋅0.20⋅10−12F⋅1200μA/V2⋅(3.3V−0.75V)=0.471 ns

then:

tr=tf=3τP=1.412 ns

31

For simplicity, let's design a symmetrical CMOS inverter, so we want τPHL=τPLH=τP=3 ns. We also require this since we want tf=tr. Then:

3ns=1.2⋅1⋅10−12F⋅1Kt(2.5V−0.6V)Kt=211μA/V2

where Kt is a placeholder for either Kn,Kp as the process is the same for both. Thus:

(W/L)N=KnKn′=211100=2.11(W/L)P=KpKp′=21140=5.28

7.4: CMOS Power Characteristics

43

a

Each gate can get:

P=100W for all gates500 million gates=200nW per gate

b

If VDD=1.8V then:

Ptotal=100W=1.8V⋅IDD⇒IDD=55.56A

47

a

Here:

Kn=15⋅100μA/V2=1500μA/V2Kp=15⋅40μA/V2=600μA/V2

so then KR=KnKp=2.5. At VM (peak current) we have both M's in saturation:

1500/2⋅μA/V2⋅(VM−0.6V)2=600/2⋅μA/V2⋅(VM−3.3V+0.6V)2

Giving:

VM≈1.414V

Plugging back in:

ID,max≈497μA

b

Doing the same process:

1500/2⋅μA/V2⋅(VM−0.6V)2=600/2⋅μA/V2⋅(VM−2.5V+0.6V)2

Giving:

VM≈1.104V

Plugging back in:

ID,max≈190μA

51

Here C=0.20 pF and VDD=2.5V. We solved this problem in HW 5 - CMOS Inverter Dynamic and Power Energy Characteristics#24. By the symmetry of the Kt's and the Vt's then our rise and fall times and similar were similar. Here:

PDP(VDD=2.5V)≥CVDD25=0.2⋅10−12F⋅(2.5V)25=250 fJPDP(VDD=2.0V)=160 fJPDP(VDD=1.8V)=130 fJ

If f=100Mhz, using τP=0.632 ns for the first, τP=0.857 ns for the second, and τ=1 ns for the latter:

P(VDD=2.5V)=CVDD2⋅f=5PDP⋅f=125μWP(VDD=2.0V)=80μWP(VDD=1.8V)=65μW

52

a

Again, just use the value from HW 5 - CMOS Inverter Dynamic and Power Energy Characteristics#29:

PDP=CVDD25=0.20⋅10−12F⋅(3.3V)25=436 fJ

b

The highest switching frequency is when ta,tb→0, so then:

T≥2tr0.8=5τP

so since τP=0.471 ns then T=2.355 ns so then fmax=425 Ghz.

c

At this highest frequency:

Pmax=5PDP⋅fmax=926μW