Modules 3 & 4 - NMOS Inverters & PMOS Review

Chapter 6.5: NMOS (+PMOS) Logic Design

We'll now try to use MOSFETS to try to design our logic gates. Recall from Modules 1 & 2 - NMOS Review#Section 4.2 NMOS Equations that the MOS device depends on:

$v_{G S}$
$v_{D S}$
Source-bulk voltage $v_{S B}$ (which changes $V_{t n}$ ).
Device parameters $K_{n}, W / L, K_{n}^{'}$

So it is now our job to choose these values such that we get the desired logic functionality we want!

Notice though that usually $V_{D D}$ (usually $V_{-}$ and $V_{+}$ ) are given values that we have to work around, so then usually the voltages are out of our control. Recall from Modules 1 & 2 - NMOS Review#6.1 Ideal Logic Gates that $V_{D D}$ was usually $5 V$ .

We first do logic design by making a simple logic inverter:

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We'll explore the intricacies of this NMOS inverter with resistor load now.

6.5.1: NMOS Inverter With Resistive Load

Recall that when we cascade inverters as we did in Modules 1 & 2 - NMOS Review#6.3 Dynamic Response of Logic Gates, we have $V_{o} = V_{H}$ when an input voltage of $V_{I} = V_{L}$ and vice versa.

Looking at Figure 6.11 seen [[Pasted image 20240117112307.png]], we use a resistor load to "pull" the output up towards the power supply $V_{D D}$ . So when the MOSFET is "off" then no current flows, so $V_{o} = V_{D D} \approx V_{H}$ , as we wanted. And when the MOSFET is "on" then $V_{o} = V_{L}$ as desired too.

We need to choose values for $R$ and $W / L$ of switching transistor $M_{S}$ such that we can meet the design specifications, letting us choose $V_{L}$ and the total power dissipation for the gate. We summarize everything below:

NMOS Inverter

When $V_{I} = V_{H}$ :

V_{o} = V_{D S} = V_{D D} - i_{D} R

And when $V_{I} = V_{L}$ :

V_{o} = V_{D D} = V_{H}

So therefore the power supply voltage $V_{D D}$ sets what a logic high $V_{H}$ is. Further, for $V_{I} = V_{L} = V_{G S}$ we require that $V_{I} < V_{t n}$ .

Design

For something like $V_{t n} = 0.6 V$ a good rule of thumb is to have $V_{L} \in (0.25 V_{t n}, 0.5 V_{t n}) = (0.15 V, 0.3 V)$ .

6.5.2: Design of the $W / L$ Ratio for $M_{S}$

$W / L$ will come from our chosen value for $V_{L}$ . Say we have $V_{t n} = 0.6 V$ , so as the design note above mentions, then $V_{L} = 0.2 V$ :

Choosing

W / L

Say $V_{t n} = 0.6 V \Rightarrow V_{L} = 0.2 V$ . Say we're given $K_{n}^{'} = 100 \frac{μ A}{V^{2}}$ . The current is determined by the power dissipation of the NMOS gate when $V_{o} = V_{L}$ . Say $P = 0.2 mW$ . Then we know that $P = V_{D D} \cdot I_{D D}$ so then:

0.2 mW = 2.5 V \cdot I_{D D} \Rightarrow I_{D D} = 80 μ A

Thus, when our $V_{I} = V_{H} = V_{D D}$ then we have $V_{o} = V_{L}$ . We use the triode drain current since $V_{G S} - V_{t n} = 2.5 V - 0.6 V = 1.9 V$ , while $v_{D S} = V_{L} = 0.2 V$ , so $V_{D S} < V_{O V}$ which gives rise to the triode behavior. Thus:

I_{D} = K_{n}^{'} {\frac{W}{L}}_{S} (v_{G S} - V_{t n} - 0.5 V_{D S}) V_{D S}

Plugging in:

80 μ A = 100 \frac{μ A}{V^{2}} (W / L)_{s} (2.5 V - 0.6 V - 0.5 \cdot 0.2 V) (0.2 V)

Thus:

80 = 36 (W / L) \Rightarrow W / L = 2.222222 \dots

6.5.3: Load Resistor Design

How do we choose $R$ ? We choose it based on when $V_{o} = V_{L}$ , which has:

R = \frac{V_{D D} - V_{L}}{I_{D D}} = \frac{2.5 V - 0.2 V}{80 μ A} = 28.8 k Ω

Choosing

R

Redesign the logic gate designed in Example 1 to operate at a power of $0.4 mW$ while maintaining $V_{L} = 0.2 V$ . Really, $P$ is getting doubled, which would double $I_{D D}$ . Thus, we expect:

160 = 36 (W / L) \Rightarrow W / L = 4.4444 . . .

Similarly, $R$ is inversely proportional to $I_{D D}$ so then $R$ gets halved to $R = 14.4 k Ω$ .

6.5.4: Load-Line Visualization

We'll look at the IV characteristic using:

V_{D S} = V_{D D} - I_{D} R

When we are in CO, we have $I_{D} = 0$ so then $V_{D S} = V_{D D} = 2.5 V$ . When we're in the triode region then we have $V_{G S} = V_{H} = 2.5 V$ so then $V_{D S} = V_{L} = 0.2 V$ . But we must have some switch in operating modes between $V_{L}$ and $V_{H}$ . We can draw the load line to visualize when this change happens:

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Here, we connect the two points described above to see where our Q-point is. In this case, the Q-point is the left point, where the slope's inverse indicates the MOSFETs load resistance.

Consult [[microelectronic-circuit-design-4th-edition-jaeger1.pdf#pages=301]] for a design process using this idea.

6.5.5: On-Resistance of the Switching Device

We can generalize this process, as we really only care when $V_{I} = V_{L}$ or $V_{H}$ , using the $R_{o n}$ as a factor here using a voltage divider:

V_{L} = V_{D D} \cdot \frac{R_{o n}}{R_{o n} + R} = V_{D D} \cdot \frac{1}{1 + \frac{R}{R_{o n}}}

where recall that $R_{o n}$ is given by Modules 1 & 2 - NMOS Review#Section 4.2 NMOS Equations, but we review here:

R_{o n} = \frac{V_{D S}}{I_{D}} = \frac{1}{K_{n} (V_{G S} - V_{t n} - \frac{V_{D S}}{2})}

So for $V_{L}$ to be small, we require that $R_{o n} << R$ . This whole $\frac{R}{R_{o n}}$ idea gives rise to the idea of ratioed logic, where we design based on this ratio, rather than the values themselves.

6.5.6: Noise Margin Analysis

Using our designs above, we can simulate or do the math ourselves and get an IV plot:

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of which now we can find the $slope = - 1$ points which give the $V_{I L}, V_{I H}, . . .$ points.

6.5.7: Calculating $V_{I L}$ and $V_{O H}$

We do an example of this now. Consider again:

V_{O} = V_{D D} - I_{D} R

When $V_{I} = V_{I L}$ we have $V_{G S}$ as small ( $V_{G S} = V_{I}$ ) and $V_{D S}$ is large (relatively speaking, since $V_{D S} = V_{D D}$ ). Thus, we are likely in the saturation region:

I_{D} = \frac{K_{n}}{2} (V_{G S} - V_{t n})^{2}, (λ = 0)

Substituting this in gives:

V_{O} = V_{D D} - \frac{K_{n}}{2} (V_{I} - V_{t n})^{2} R

We want to find the slope at this point to get the -1 slope points:

\frac{\partial v_{o}}{\partial v_{i}} = - K_{n} (V_{I} - V_{t n}) R

We know these points have -1 slope so:

- 1 = - K_{n} (V_{I} - V_{t n}) R \Rightarrow V_{I L} = \frac{1}{K_{n} R} + V_{t n}

where plugging this back in as $V_{I}$ from our $V_{O}$ equation:

V_{O H} = V_{D D} - \frac{1}{2 K_{n} R}

We usually note that $1 / (K_{n} R)$ has units of voltage, so it's the ratio of the transistor's transconductance parameter (say that 10 times fast).

6.5.8: Calculating $V_{I H}$ and $V_{O L}$

Likewise, we do the same for the other 2 parameters. When $V_{I} = V_{I H}$ then $V_{G S}$ is large and $V_{D S}$ is small so we are in the triode region. Thus:

I_{D} = K_{n} (V_{G S} - V_{t n} - (V_{D S} / 2)) V_{D S}

We substitute in back into our $V_{O}$ generic equation to get:

V_{O} = V_{D D} - K_{N} V_{D S} (V_{G S} - V_{t n} - V_{O} / 2) R

We can do some rearranging to get:

\frac{V_{O}^{2}}{2} - V_{O} [V_{I} - V_{t n} + \frac{1}{K_{n} R}] + \frac{V_{D D}}{K_{n} R} = 0

We solve for $V_{o}$ and set the derivative of $V_{o}$ to -1 for $V_{I} = V_{I H}$ to get:

V_{I H} = V_{t n} - \frac{1}{K_{n} R} + 1.63 \sqrt{\frac{V_{D D}}{K_{n} R}}

and:

V_{O L} = \sqrt{\frac{2 V_{D D}}{3 K_{n} R}}

Calculating

N M_{H}

and

N M_{L}

We can substitute our values into our $N M_{H}$ and $N M_{L}$ equations described at Modules 1 & 2 - NMOS Review#6.3.1 Rise and Fall Time to get:

N M_{H} = V_{D D} - V_{t n} + \frac{1}{2 K_{n} R} - 1.63 \sqrt{\frac{V_{D D}}{K_{n} R}}

and:

N M_{L} = V_{t n} + \frac{1}{K_{n} R} - \sqrt{\frac{2 V_{D D}}{3 K_{n} R}}

I'd recommend not doing it this way and instead using the equations defined in terms of $V_{O L}, V_{O H}, . . .$ and finding those instead using the above equations.

6.5.9: Load Resistor Problems

Consider a rectangular block of semiconductor material:

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The resistance is given by:

R = \frac{ρ L}{A} = \frac{ρ L}{t W}

For say a resistor like the $28.8 k Ω$ we usually we, we require the $L / W$ ratio to be:

L / W = \frac{R t}{ρ} = \frac{2.88 k | O m e g a \cdot 0.1 μ m}{0.001 Ω c m} = 2880 / 1

So if the $W$ was some minimum line width of $1 μ m$ , then $L = 2800 μ m$ . The area would be $2800 μ m^{2}$ while the transistor itself is only $W / L = 2.22$ which wouldn't be acceptable.

6.6: Transistor Alternatives to the Load Resistor

The $R$ in our previous calculations just sucked! How about we remove it? Change $R$ with some new NMOS transistor $M_{2}$ .

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(a) and (b) are always either turned always off or on. But (c-e) have properties that'll be interesting to us.

6.6.1: The NMOS Saturated Load Inverter

First consider (c). Here $V_{D S} = V_{G S}$ in $M_{L}$ . We refer to this as a saturated load inverter.

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Notice:

The $p$ -type substrate is common between the $M_{S}, M_{L}$ .
We have $V_{B} = 0 V$ (ie: connect it to ground), so then $V_{S B} = 0$ for $M_{S}$ , but for $M_{L}$ we have $V_{S B} = V_{o}$ . This will affect $V_{t n}$ for both $M_{S}, M_{L}$ so then we denote each separately as $V_{t n S}$ and $V_{t n L}$ .

Consider for our cases that $I_{D} = 80 μ A$ and $V_{D D} = 2.5 V$ and $V_{L} = 0.2 V$ . We know that $M_{L}$ has to operate in the saturation region (as $V_{G S} = V_{D S}$ so then $V_{G S} - V_{t n} = V_{D S} - V_{t n} < V_{D S}$ for $V_{t n} > 0$ ), so then:

I_{D} = \frac{K_{n}^{'}}{2} \cdot W / L \cdot (V_{G S} - V_{t n L})^{2}

We know that when $V_{L} = V_{o}$ then $V_{D S, S} = 0.2 V$ and $V_{D S, L} = 2.3 V$ . Other values are in Figure 6.19 above. But we need to get $V_{t n L}$ first, which is given by:

V_{t n} = V_{T O} + γ (\sqrt{V_{S B} + 2 ϕ_{F}} - \sqrt{2 ϕ_{F}})

We usually are just given these values from a table, so we'll use:

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Cool! So then:

V_{t n L} = 0.6 + 0.5 (\sqrt{0.2 + 0.6} - \sqrt{0.6}) = 0.66 V

Now solve for $W / L$ in the current equation above:

(W / L)_{L} = \frac{2 I_{D}}{K_{n}^{'} (V_{G S} - V_{t n L})^{2}} = \frac{2 \cdot 80 μ A}{100 \frac{μ A}{V^{2}} (2.3 V - 0.66 V)^{2}} = \frac{1}{1.68}

So now the $L$ has to be bigger than $W$ , but we still use the larger side as the measure of size. With that, then the gate area is $M_{L} = 1.68 μ m^{2}$ .

Calculation of $V_{H}$

We'll find that the value of $V_{H} \neq V_{D D}$ sadly. Consider the following circuit:

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Consider $V_{I} = V_{L}$ , so then $M_{S}$ is turned off. But $V_{O}$ will approach $V_{D D} - V_{T O}$ so we'd reach $1.9 V$ rather than $2.5 V$ . But with body effect we consider the entirety of $V_{t n L}$ which is lower than $V_{T O}$ .

Really, we use the same $V_{t n}$ equation as before, so for instance:

V_{t n L} = 0.6 V + 0.5 (\sqrt{0.2 V + 0.6 V} - \sqrt{0.6}) = 0.66 V

where $V_{T O} = 0.6 V, γ = 0.5, V_{S B} = 0.2 V, 2 ϕ_{F} = 0.6 V$ as per usual.

Calculation of $V_{H}$

is just:

V_{H} = V_{D D} - V_{t n L} = V_{D D} - [V_{T O} + γ (\sqrt{V_{H} + 2 ϕ_{F}} - \sqrt{2 ϕ_{F}})]

where we do some solving via using a calculator to find the intersection for $V_{H}$ .

Calculation of $(W / L)_{S}$

For the switching transistor $M_{S}$ calculating the ratio is via determining the region of operation based on given design values. For triode:

(W / L)_{s} = \frac{i_{D}}{K_{n}^{'} V_{D S} (V_{G S} - V_{t n S} - \frac{V_{D S}}{2})}

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Notice here $V_{H} = V_{O H}$ as it suddenly gives to a negative slope.

6.6.2: NMOS Inverter w/ A Linear Load Device

Consider (d) now. The gate is connected to a $V_{G G}$ , which is normally chosen to be at least one threshold voltage greater than the supply voltage $V_{D D}$ :

V_{G G} \geq V_{D D} + V_{t n L}

Again, like the previous analysis, consider $V_{H}$ as equal to $V_{D D}$ , as:

\begin{array}{r} V_{D S} = 0 \Rightarrow V_{D S} = V_{D D} - V_{H} \end{array}

We can check the region of operation by seeing when $V_{D S} \circ V_{G S} - V_{t n L}$ :

\begin{aligned} V_{G S} - V_{t n L} & = V_{G G} - V_{o} - V t n L \\ \geq V_{D D} + V_{t n L} - V_{o} - V_{t n L} \\ \geq V_{D D} - V_{o} \end{aligned}

but since $V_{D S} = V_{D D} - V_{o}$ then always $V_{D S} \leq V_{G S} - V_{t n L}$ we are always in the triode region. As before we can solve for the $W / L$ ratios for both MOSFETs. We know that $V_{H} = V_{D D} = 2.5 V$ . We can use a graph to estimate $V_{I L}, V_{I H}, . . .$

6.6.3: NMOS Inverter w/ Depletion-Mode Load

Consider (a) now. Notice that since $V_{t n}$ is always negative, as the $V_{O V}$ typically is negative for depletion-mode NMOSFETs (not enhancement mode), so then we are usually in saturation via:

V_{D S} \geq V_{G S} - V_{t n L} = - V_{t n L}

so we require for that state that $V_{D S} \geq | V_{t n L} |$ .

Design of $W / L$ ratios for $M_{L}$ .

Assume $V_{D D} = 2.5 V$ , $V_{L} = 0.2 V$ and $V_{t n L} = - 1 V$ . When $V_{o} = V_{L} = 0.2 V$ then $V_{D S} = 2.3 V \geq - V_{t n L} = 1 V$ . So the MOS operates in saturation, then:

I_{D L} = \frac{K_{n}^{'}}{2} W / L \cdot (V_{G S L} - V_{t n L})^{2} = \frac{K_{n}^{'}}{2} W / L \cdot (V_{t n L})^{2}

if there's body effect we account for that in our $V_{t n L}$ calculation:

V_{t n L} = - 1 + 0.5 (\sqrt{0.2 + 0.6} - \sqrt{0.6}) = - 0.94 V

Design of $W / L$ ratios for $M_{S}$ .

When $V_{I} = V_{H} = V_{D D}$ then the bottom MOS is in saturation, which follows the exact same analysis as we did in Modules 3 & 4 - NMOS Inverters & PMOS Review#6.5.3 Load Resistor Design.

Noise Margin Analysis

Again, the calculations for finding $N M_{L}$ and $N M_{H}$ are tedious, so just use a SPICE simulation or some graph.

4.3: PMOS Review

PMOS Characteristics are derived almost exactly as their Modules 1 & 2 - NMOS Review#Section 4.2 NMOS Equations counterparts, except for an extra $-$ sign here and there:

PMOS Equations

For all regions:

K_{p} = K_{p}^{'} \cdot W / L, K_{p}^{'} = μ_{p} C_{o x}^{″}, I_{G} = 0, I_{B} = 0

Cutoff Region ( $V_{G S} \geq V_{t p}$ ):

I_{D} = 0

Triode Region ( $V_{G S} < V_{t p}$ and $0 \leq | V_{D S} | \leq | V_{G S} - V_{t p} |$ ):

I_{D} = K_{p} (V_{G S} - V_{t p} - \frac{V_{D S}}{2}) V_{D S}

Saturation Region ( $V_{G S} < V_{t p}$ and $| V_{D S} | \geq | V_{G S} - V_{t p} | \geq 0$ ):

I_{D} = \frac{K_{p}}{2} (V_{G S} - V_{t p})^{2} (1 + λ | V_{D S} |)

Threshold Voltage:

V_{t p} = V_{T O} - γ (\sqrt{V_{B S} + 2 ϕ_{F}} - \sqrt{2 ϕ_{F}})

Enhancement Mode $\to V_{t p} < 0$ . Depletion Mode $V_{t p} \geq 0$ .

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Chapter 6.5: NMOS (+PMOS) Logic Design

6.5.1: NMOS Inverter With Resistive Load

6.5.2: Design of the W/L Ratio for MS

6.5.3: Load Resistor Design

6.5.4: Load-Line Visualization

6.5.5: On-Resistance of the Switching Device

6.5.6: Noise Margin Analysis

6.5.7: Calculating VIL and VOH

6.5.8: Calculating VIH and VOL

6.5.9: Load Resistor Problems

6.6: Transistor Alternatives to the Load Resistor

6.6.1: The NMOS Saturated Load Inverter

Calculation of VH

Calculation of VH

Calculation of (W/L)S

6.6.2: NMOS Inverter w/ A Linear Load Device

6.6.3: NMOS Inverter w/ Depletion-Mode Load

Design of W/L ratios for ML.

Design of W/L ratios for MS.

Noise Margin Analysis

4.3: PMOS Review

6.5.2: Design of the $W / L$ Ratio for $M_{S}$

6.5.7: Calculating $V_{I L}$ and $V_{O H}$

6.5.8: Calculating $V_{I H}$ and $V_{O L}$

Calculation of $V_{H}$

Calculation of $V_{H}$

Calculation of $(W / L)_{S}$

Design of $W / L$ ratios for $M_{L}$ .

Design of $W / L$ ratios for $M_{S}$ .